A quick look at the schematics for the Elbert V2 development board show that the seven segment displays are common anode connected and driven by three PNP transistors. These in turn are connected to the FPGA pins and 3.3V and GND. Some people would say the seven segment displays are 'multiplexed'.
Anyway if the connections P120, P121 and P124 are not controlled and in a strange state then the seven segment displays will ghost (be slightly on). So to prevent this we need to ensure that the FPGA drives the pins into a 'High' state. This means that the PNP transistors are not biased on and the seven segments stay off.
So in order to do that we need to add three extra outputs to any project, set them high and reference them in the user constraints file. To demonstrate I'm using the code from the previous VHDL example:
Elbert v2 VHDL Tutorial
Load up Xilinx ISE project navigator, load the project and add the following to the code:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Switch_LEDS is Port ( Switch_One : in STD_LOGIC; Switch_Two : in STD_LOGIC; LED_One : out STD_LOGIC; LED_Two : out STD_LOGIC; Seven_Segment_Transistor_One : out STD_LOGIC; Seven_Segment_Transistor_Two : out STD_LOGIC; Seven_Segment_Transistor_Three : out STD_LOGIC); end Switch_LEDS; architecture Behavioral of Switch_LEDS is begin LED_One <= NOT Switch_One; LED_Two <= NOT Switch_Two; Seven_Segment_Transistor_One <= '1'; --Turn PNP transistor off Seven_Segment_Transistor_Two <= '1'; --Turn PNP transistor off Seven_Segment_Transistor_Three <='1'; --Turn PNP transistor off end Behavioral;
Next we need to update the user constraints file with the information showing where the pins connecting the FPGA to the PNP Transistors. Copy and paste the code below into the UCF file:
############################################################################ # Switches ############################################################################ NET "Switch_One" LOC = P80 | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "Switch_Two" LOC = P79 | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; ############################################################################ # PULLUP Resistors - Enable Pullup resistors ############################################################################ NET "Switch_One" PULLUP ; NET "Switch_Two" PULLUP ; ############################################################################ # LED ############################################################################ NET "LED_Two" LOC = P54 | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "LED_One" LOC = P55 | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "Seven_Segment_Transistor_One" LOC = P124 | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "Seven_Segment_Transistor_Two" LOC = P121 | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "Seven_Segment_Transistor_Three" LOC = P120 | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
Once we have done that we can save all of the files and rebuild our project in Xilinx ISE Project Manager:After that generate and new programming file and upload it to the Elbert V2 board and - Success!
That's all for now - Langster!
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