Monday, 30 May 2016

Generating more square wave pulses using counters on the Mimas V2

In a previous post I wrote about how it is possible to generate a 1 Hz clock pulse using the 100 MHz source clock and a 27 bit counter.  This post continues on that theme but this time we are going to generate different clock pulses and more of them!

If people did not see the previous post it's available here:

A simple post on counters...

Load up the project from the previous post and lets modify it.  What we are going to do is add more LED outputs and then use code we wrote to flash them at faster and faster rates:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity LED_flasher is
    Port ( clock_in : in  STD_LOGIC;
           LED_1 : out  STD_LOGIC;
 LED_2 : out  STD_LOGIC;
 LED_3 : out  STD_LOGIC;
 LED_4 : out  STD_LOGIC;
 LED_5 : out  STD_LOGIC;
 LED_6 : out  STD_LOGIC;
 LED_7 : out  STD_LOGIC;
 LED_8 : out  STD_LOGIC);
 
end LED_flasher;

architecture Behavioral of LED_flasher is

signal counter : STD_LOGIC_VECTOR(27 downto 0):= (others=>'0');

begin

process (clock_in) is

begin

if rising_edge(clock_in) then
counter <= counter + 1;
end if;

end process;

LED_1 <= NOT counter(27);
LED_2 <= NOT counter(26);
LED_3 <= NOT counter(25);
LED_4 <= NOT counter(24);
LED_5 <= NOT counter(23);
LED_6 <= NOT counter(22);
LED_7 <= NOT counter(21);
LED_8 <= NOT counter(20);

end Behavioral;

The above code basically works in exactly the same way as the previous code did.  The only difference is that we have more outputs and we are displaying the results from the counting at different stages on the LEDS.  So in the previous code we calculated that a count of 27 bits divided a 100 MHz source clock to 1 Hz.  Therefore a count of 26 bits will flash an LED every half second, a count of 25 bits will flash an LED every 0.25 of a second and so on...

We will also need to update the user constraints file to account for the extra outputs:

#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++#
# This file is a .ucf for Mimas V2                                               #
# To use it in your project :                                                    #
# * Remove or comment the lines corresponding to unused pins in the project      #
# * Rename the used signals according to the your project                        #
#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++#

CONFIG VCCAUX = "3.3" ;

NET "clock_in" LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz;

###################################################################################
#                                LEDs                                             #
################################################################################### 
   
   NET "LED_1" LOC = P15  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
   NET "LED_2" LOC = P16  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
   NET "LED_3" LOC = N15  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
   NET "LED_4" LOC = N16  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
   NET "LED_5" LOC = U17  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
   NET "LED_6" LOC = U18  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
   NET "LED_7" LOC = T17  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
   NET "LED_8" LOC = T18  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;

Save the project, build the updated bit file and then upload the code to the Mimas V2 board.  Here is a video of the board in action:


There are even more things that could be done with this.  We could use the external outputs to provide the other clock divisions present.  There are more than enough outputs available.  What this project clearly shows is that it is quite simple to generate multiple clock streams simultaneously using an FPGA.

Here is the source code in case it's needed:

Square Pulses Source Code

That's all for now - Langster!